1. Field of the Invention
The present invention relates to a synchronizing circuit in a display or the like for obtaining a horizontal synchronizing signal and a vertical synchronizing signal from a composite synchronizing signal.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a conventional synchronizing circuit designed to obtain a horizontal synchronizing signal and a vertical synchronizing signal from a composite synchronizing signal.
A phase locked loop (PLL) circuit 21 receives a composite synchronizing signal SYNa from a terminal TSYN. The PPL Circuit 21 generates both a clock CKa synchronized with the horizontal synchronizing component of the composite synchronizing signal SYNa, and a reset pulse RESa for resetting a counter 22 of a next stage.
The counter 22 is a circuit for generating a horizontal synchronizing signal HSa synchronized with the horizontal synchronizing component of the composite synchronizing signal SYNa and delivering to a terminal THS, by counting the clocks CKa as being reset by the reset pulse RESa.
A vertical synchronizing component separating circuit 23 receives the composite synchronizing signal SYNa from the terminal TSYN, and generates a pulse VSa synchronized with the vertical synchronizing component in the composite synchronizing signal SYNa.
A vertical synchronizing signal generating circuit 24 converts the pulse YSa generated in the vertical synchronizing component separating circuit 2S into a vertical synchronizing signal VHa synchronized with the horizontal synchronizing signal HSa generated in the counter 22, and delivers the signal VHa to the terminal TVH.
In the case of a composite synchronizing signal SYNa recorded in a video tape, a signal for prevention of copying (hereinafter called a copy guard signal) is sometimes added between signal synchronizing signals in the vertical blanking period. In the conventional synchronizing circuit as described above, to obtain the horizontal synchronizing signal HSa and vertical synchronizing signal VHa from such composite synchronizing signal SYNa, the clock CKa and reset pulse RESa generated in the PLL circuit 21 are disturbed by the copy guard signal. The horizontal synchronizing signal HSa generated in the counter 22 is also disturbed, and the picture cannot be displayed normally.
That is, the copy guard signal is standardized so as to be added from a specific period after the beginning of the vertical synchronizing signal till two horizontal periods before start of the video signal. But the disturbance of the horizontal synchronizing signal HSa due to this copy guard signal continues for several horizontal periods after start of video signal, and a picture disturbance appears in the upper part of the display image.
Because the PLL circuit 21 is used for matching the phase of the horizontal synchronizing signal HS (generated with the composite synchronizing signal SYNa), the horizontal synchronizing signal HSa is disturbed even after start of the video signal. More specifically, when the reaction speed of the PLL circuit 21 is slow, the disturbance of the horizontal synchronizing signal HSa continues for a longer period. If the reaction speed is too fast, other troubles occur, and it is otherwise impossible to avoid disturbance of the picture by adjusting the reaction speed of the PLL circuit 21.
SUMMARY OF THE INVENTION
A primary object of the invention to present a synchronizing circuit capable of obtaining a horizontal synchronizing signal and a vertical synchronizing signal which does not disturb the image from a composite synchronizing signal, even if a specific signal such as copy guard signal is added between horizontal synchronizing signals within the composite synchronizing signal.
To achieve the above object, the invention presents a synchronizing circuit for obtaining a horizontal synchronizing signal and a vertical synchronizing signal from a composite synchronizing signal comprising a mask circuit, a judging circuit, and a discriminative circuit.
The mask circuit masks the composite synchronizing signal and obtains a masked composite synchronizing signal removing a specific signal (the specific signal having been added between horizontal synchronizing signals in the composite synchronizing signal) and the addition period of this specific signal having been limited in a specific period by reference to the vertical synchronizing signal.
The judging circuit judges whether noise is contained in the composite synchronizing signal.
The discriminating circuit receives either the composite synchronizing signal (not passing through the mask circuit when it is judged that the noise signal is contained by the judging circuit) or the masked composite synchronizing signal (obtained from the mask circuit when it is judged that noise signal is not contained by the judging circuit), as the composite synchronizing signal (from which the horizontal synchronizing signal and vertical synchronizing signal are obtained).
Thus, according to the synchronizing circuit of the invention, when noise is not contained in the composite synchronizing signal, the masked composite synchronizing signal (being rid of specific signal such as copy guard signal through the mask circuit) is used. When noise is contained in the composite synchronizing signal, the composite synchronizing signal (not passing through the mask circuit) is used. The horizontal synchronizing signal and vertical synchronizing signal are obtained from the used signal. Therefore as far as the composite synchronizing signal is free from noise signal, even if the copy guard signal is added to the composite synchronizing signal, the horizontal synchronizing signal and a vertical synchronizing signal which does not disturb the image is obtained.
The invention is characterized in that the discriminating circuit comprises a PLL circuit and a first counter for generating a horizontal synchronizing signal, and a vertical synchronizing component separating circuit and a vertical synchronizing signal generating circuit for generating a vertical synchronizing signal.
The PLL circuit generates a clock synchronized with the horizontal synchronizing component and a reset pulse for resetting the first counter, on the basis of the input composite synchronizing signal.
The first counter counts the clocks, and generates a horizontal synchronizing signal and a first pulse for showing the time after the addition period of the specific signal.
The vertical synchronizing component separating circuit generates a second pulse synchronized with the vertical synchronizing component to the basis of the input composite synchronizing signal.
The vertical synchronizing signal generating circuit converts the second pulse into a vertical synchronizing signal synchronized with the horizontal synchronizing signal.
Also the invention is characterized in that the mask circuit comprises a second counter, a latch circuit, and a gate circuit.
The second counter counts the input composite synchronizing signals, being reset by the first pulse from the first counter, and delivers a third pulse which is changed in a period from the counting of 2 to 3.
The latch circuit delivers a fourth pulse which is changed in the period from rise of the third pulse to fall of the first pulse.
The gate circuit masks the composite synchronizing signal fed by the fourth pulse and delivers a masked composite synchronizing signal.
Furthermore, the invention is characterized in that the judging circuit comprises a third counter, a gate circuit, a noise judging circuit, a latch circuit, and an OR gate.
The third counter counts the horizontal synchronizing signals which are outputs from the first counter. The third counter delivers: (1) a fifth pulse (which is changed in the period from the counting 0 to 1); (2) a sixth pulse (which is changed in the period from the counting m of counting the first horizontal synchronizing signal of the horizontal synchronizing signals having the specific signal added in the meantime till the counting of n of counting the last horizontal synchronizing signal); and (3) a seventh pulse (which is changed in the period from the counting of n to n+l).
The gate circuit delivers the composite synchronizing signal as it is when the fifth pulse is fed in the low level period.
The noise judging circuit counts the outputs from the gate circuit, and delivers a pulse to indicate noise state when reaching a predetermined counting c.
The latch circuit delivers a pulse which is at high level in the period from fall of the output pulse from the noise judging circuit till fall of the seventh pulse from the third counter.
The OR gate circuit delivers an OR signal of the sixth pulse from the third counter and the pulse from the latch circuit.
Also the invention is characterized in that the discriminating circuit comprises a changeover circuit which receives the input composite synchronizing signal and the masked composite synchronizing signal from the mask circuit, and selects the masked composite synchronizing signal or the input composite synchronizing signal on the basis of the OR signal from the OR gate circuit, and applies to the PLL circuit.